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74AC11008DR Datasheet
74AC11008DR Cross Reference
74AC11008DR Schematic
74AC11008DR Distributor
74AC11008DR Datenblatt
74AC11008DR RoHS
74AC11008DR Equivalent
74AC11008DR Application Notes
74AC11008DR Data Sheet
74AC11008DR component
74AC11008DR Fiche Technique
74AC11008DR Circuit
Flow-Through Architecture Optimizes PCB Layout
Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise
EPICE (Enhanced-Performance Implanted CMOS) 1-mm Process
500-mA Typical Latch-Up Immunity at 125°C
Package Options Include Plastic Small-Outline (D) and Thin Shrink Small-Outline (PW) Packages, and Standard Plastic 300-mil DIPs (N)
description
This device contains four independent 2-input AND gates. It performs the Boolean function Y A • B or Y AB in positive logic.
The 74AC11008 is characterized for operation from –40°C to 85°C.
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74AC11008DR.pdf
