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  •   AT89C55WD Datasheet
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  • AT  -  Series DataSheet
    AT89C55WD  -  8-bit Microcontroller with 20K Bytes Flash  -  Atmel  -  8051


    Features
    • Compatible with MCS®-51 Products
    • 20K Bytes of Reprogrammable Flash Memory
    • Endurance: 10,000 Write/Erase Cycles
    • 4V to 5.5V Operating Range
    • Fully Static Operation: 0 Hz to 33 MHz
    • Three-level Program Memory Lock
    • 256 x 8-bit Internal RAM
    • 32 Programmable I/O Lines
    • Three 16-bit Timer/Counters
    • Eight Interrupt Sources
    • Programmable Serial Channel
    • Low-power Idle and Power-down Modes
    • Interrupt Recovery from Power-down Mode
    • Hardware Watchdog Timer
    • Dual Data Pointer
    • Power-off Flag
    • Green (Pb/Halide-free) Packaging Option
     Description
    The AT89C55WD is a low-power, high-performance CMOS 8-bit microcontroller with 20K bytes of Flash programmable read only memory and 256 bytes of RAM. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry standard 80C51 and 80C52 instruction set and pinout. The on-chip Flash allows the program memory to be user programmed by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C55WD is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.
    The AT89C55WD provides the following standard features: 20K bytes of Flash, 256 bytes of RAM, 32 I/O lines, three 16-bit timer/counters, a six-vector, two-level interrupt architecture, a full-duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89C55WD is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset.



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