AT  -  Series DataSheet
AT89LS52  -  8-bit Low-Voltage Microcontroller with 8K Bytes In-System Programmable Flash  -  Atmel  -  8051

Features
• Compatible with MCS®-51 Products
• 8K Bytes of In-System Programmable (ISP) Flash Memory
– Endurance: 10,000 Write/Erase Cycles
• 2.7V to 4.0V Operating Range
• Fully Static Operation: 0 Hz to 16 MHz
• Three-level Program Memory Lock
• 256 x 8-bit Internal RAM
• 32 Programmable I/O Lines
• Three 16-bit Timer/Counters
• Eight Interrupt Sources
• Full Duplex UART Serial Channel
• Low-power Idle and Power-down Modes
• Interrupt Recovery from Power-down Mode
• Watchdog Timer
• Dual Data Pointer
• Power-off Flag
• Flexible ISP Programming (Byte and Page Modes)
• Green (Pb/Halide-free) Packaging Option
Description
The AT89LS52 is a low-voltage, high-performance CMOS 8-bit microcontroller with 8K bytes of in-system programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic chip, the Atmel AT89LS52 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.
The AT89LS52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89LS52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset.