AT  -  Series DataSheet
AT91CAP7E  -  Customizable Microcontroller  -  Atmel  -  ARM

Features
• Incorporates the ARM7TDMI® ARM® Thumb® Processor
– 72 MIPS at 80MHz
– EmbeddedICE™ In-circuit Emulation, Debug Communication Channel Support
• Additional Embedded Memories
– One 256 Kbyte Internal ROM, Single-cycle Access at Maximum Matrix Speed
– 160 Kbytes of Internal SRAM, Single-cycle Access at Maximum Processor or Matrix Speed (Configured in blocks of 96 KB and 64 KB with separate AHB slaves)
• External Bus Interface (EBI)
– Supports SDRAM, Static Memory, NAND Flash/SmartMedia® and CompactFlash®
• USB 2.0 Full Speed (12 Mbits per second) Device Port
– On-chip Transceiver, 2,432-byte Configurable Integrated DPRAM
• FPGA Interface
– High Connectivity for up to 2 AHB Masters and 4 dedicated/16 muxed Slaves
• 10-bit Analog to Digital Converter (ADC)
– Up to 8 multiplexed channels
– 440 kSample / s
• Bus Matrix
– Four-layer, 32-bit Matrix
• Fully-featured System Controller, including
– Reset Controller, Shut Down Controller
– Twenty 32-bit Battery Backup Registers for a Total of 80 Bytes
– Clock Generator
– Advanced Power Management Controller (APMC)
– Advanced Interrupt Controller and Debug Unit
– Periodic Interval Timer, Watchdog Timer and Real-Time Timer
• Boot Mode Select Option and Remap Command
• Reset Controller
– Based on Two Power-on Reset Cells, Reset Source Identification and Reset Output Control
• Shut Down Controller
– Programmable Shutdown Pin Control and Wake-up Circuitry
• Clock Generator (CKGR)
– 32768Hz Low-power Oscillator on Battery Backup Power Supply, Providing a Permanent Slow Clock
– Internal 32kHz RC oscillator for fast start-up
– 8 to 16 MHz On-chip Oscillator, 50 to 100 MHz PLL, and 80 to 240 MHz PLL
• Advanced Power Management Controller (APMC)
– Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities
– Four Programmable External Clock Output Signals
• Advanced Interrupt Controller (AIC)
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– Two External Interrupt Sources and one Fast Interrupt Source, Spurious interrupt protected
• Debug Unit (DBGU)
– 2-wire UART and Support for Debug Communication Channel, Programmable ICE Access Prevention
• Periodic Interval Timer (PIT)
– 20-bit interval Timer plus 12-bit interval Counter
• Watchdog Timer (WDT)
– Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock
• Real-Time Timer (RTT)
– 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler
• Two 32-bit Parallel Input/Output Controllers (PIOA and PIOB)
– 32 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os each
– Input Change Interrupt Capability on Each I/O Line
– Individually Programmable Open-drain, Pull-up Resistor, Bus Holder and Synchronous Output
• 22 Peripheral DMA Controller Channels (PDC)
• Two Universal Synchronous/Asynchronous Receiver Transmitters (USART)
– Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation, Manchester Encoding/Decoding
• Master/Slave Serial Peripheral Interface (SPI)
– 8- to 16-bit Programmable Data Length, External Peripheral Chip Select
– Synchronous Communications at up to 80Mbits/sec
• One Three-channel 16-bit Timer/Counters (TC)
– Three External Clock Inputs, Two multi-purpose I/O Pins per Channel
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
• IEEE 1149.1 JTAG Boundary Scan on All Digital Pins
• Required Power Supplies:
• 1.08V to 1.32V for VDDCORE and VDDBU
• 1.08V to 1.32V for VDDOSC, VDDOSC32, and VDDPLLB
• 3.0V to 3.6V for VDDPLLA and VDDIO
• 3.0V to 3.6V for AVDD (ADC)
• Package Options: 144 LQFP, 176 LQFP, 208 PQFP, 144 LFBGA, 176TFBGA, 208 TFBGA, 225 LFBGA

Description
The AT91CAP7E semi-custom System on a Chip (SoC) is a microcontroller with a special interface that allows logic in an external FPGA to be mapped directly onto its internal Amba High-speed Bus (AHB). This FPGA interface includes multiple master and slave channels providing much greater bus bandwidth for data passing between the microcontroller and an FPGA than traditional interface methods using general purpose I/O or external memory interfaces. The AT91CAP7E includes an ARM7TDMI core with the AHB, on-chip ROM, SRAM, a full-featured system controller, and various general-purpose peripherals accessible via the Amba Peripheral Bus (APB). It is implemented in a 130 nm CMOS 1.2V process and supports 3.3V I/O.
The AT91CAP7E is built upon Atmel’s AT91CAP7S customizablemicrocontroller with up to 450 Kgates of metal programmable (MP) logic. The FPGA Interface is implemented inthe MP block and makes use of MP I/O’s available on the AT91CAP7S giving customers not only an efficient, powerful FPGA interface on a standard microcontroller, but also an excellent platform for emulating their own AT91CAP7S-based designs.