AT  -  Series DataSheet
ATtiny84  -  8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash,Automotive  -  Atmel  -  8051

Features
• High Performance, Low Power AVR® 8-Bit Microcontroller
• Advanced RISC Architecture
– 120 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
• Non-volatile Program and Data Memories
– 2/4/8K Byte of In-System Programmable Program Memory Flash (ATtiny24/44/84) Endurance: 10,000 Write/Erase Cycles
– 128/256/512 Bytes In-System Programmable EEPROM (ATtiny24/44/84) Endurance: 100,000 Write/Erase Cycles
– 128/256/512 Bytes Internal SRAM (ATtiny24/44/84)
– Programming Lock for Self-Programming Flash Program and EEPROM Data Security
• Peripheral Features
– Two Timer/Counters, 8- and 16-bit counters with two PWM Channels on both
– 10-bit ADC 8 single-ended channels 12 differential ADC channel pairs with programmable gain (1x, 20x) Temperature Measurement
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Universal Serial Interface
• Special Microcontroller Features
– debugWIRE On-chip Debug System
– In-System Programmable via SPI Port
– External and Internal Interrupt Sources
– Pin Change Interrupt on 12 pins
– Low Power Idle, ADC Noise Reduction, Standby and Power-down Modes
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit
– Internal Calibrated Oscillator
– On-chip Temperature Sensor
• I/O and Packages
– 14-pin SOIC, 20-pin QFN/MLF: Twelve Programmable I/O Lines
• Operating Voltage:
– 2.7 - 5.5V for ATtiny24/44/84
• Speed Grade
– ATtiny24/44/84: 0 - 8 MHz @ 2.7 - 5.5V, 0 - 16 MHz @ 4.5 - 5.5V
• Automotive Temperature Range
• Low Power Consumption
– Active Mode: 1 MHz, 2.7V: 800 μA
– Power-down Mode: 2.7V: 2.0 μA
The ATtiny24/44/84 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny24/44/84 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.