GAL  -  Series DataSheet
GAL26CV12B-15LJ  -  High Performance E2CMOS PLD Generic Array Logic  -  Lattice Semiconductor Corporation  -  GAL

Features
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 7.5 ns Maximum Propagation Delay
— Fmax = 142.8 MHz
— 4.5ns Maximum from Clock Input to Data Output
— TTL Compatible 16 mA Outputs
— UltraMOS® Advanced CMOS Technology
• ACTIVE PULL-UPS ON ALL PINS
• LOW POWER CMOS
— 90 mA Typical Icc
• E2 CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• TWELVE OUTPUT LOGIC MACROCELLS
— Uses Standard 22V10 Macrocells
— Maximum Flexibility for Complex Logic Designs
• PRELOAD AND POWER-ON RESET OF REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION

Description
The GAL26CV12, at 7.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance 28-pin PLD available on the market. E2 technology offers high speed (<100ms) erase times, providing the ability to reprogram or reconfigure the device quickly and efficiently.
Expanding upon the industry standard 22V10 architecture, the GAL26CV12 eliminates the learning curve typically associated with using a new device architecture. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. The GAL26CV12 OLMC is fully compatible with the OLMC in standard bipolar and CMOS 22V10 devices.
Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.