General Description
1.1 Introduction
The MC68HC908EY16 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types.
The information contained in this document pertains to the MC68HC908EY8 with the exceptions noted in Appendix A MC68HC908EY8.
1.2 Features
For convenience, features have been organized to reflect:
• Standard features of the MC68HC908EY16
• Features of the CPU08
Standard features of the MC68HC908EY16 include:
• High-performance M68HC08 architecture optimized for C-compilers
• Fully upward-compatible object code with M6805, M146805, and M68HC05 Families
• 8-MHz internal bus frequency at 5V
• Internal oscillator requiring no external components:
– Software selectable bus frequencies
– 25 percent accuracy with a trimming capability of better than 1 percent
– Clock monitor
– Option to allow use of external clock source or external crystal/ceramic resonator
• 15,872 bytes of on-chip FLASH memory with in-circuit programming
• FLASH program memory security(1)
• 512 bytes of on-chip random-access memory (RAM)
• Low voltage inhibit (LVI) module
• Internal clock generator module (ICG)
• Two 16-bit, 2-channel timer (TIMA and TIMB) interface modules with selectable input capture, output compare, and pulse-width modulation (PWM) capability on each channel
• 8-channel, 10-bit successive approximation analog-to-digital converter (ADC)
• Enhanced serial communications interface module (ESCI) for local interconnect network (LIN) connectivity
• Serial peripheral interface (SPI)
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users.
General Description
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
20 Freescale Semiconductor
• Timebase Module (TBM)
• 5-bit keyboard interrupt (KBI) with wakeup feature
• 24 general-purpose input/output (I/O) pins
• External asynchronous interrupt pin with internal pullup (IRQ)
• System protection features:
– Optional computer operating properly (COP) reset
– Illegal opcode detection with reset
– Illegal address detection with reset
• 32-pin quad flat pack (QFP) package
• Low-power design; fully static with stop and wait modes
• Internal pullups on IRQ and RST to reduce customer system cost
• Standard low-power modes of operation:
– Wait mode
– S
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