Features
· Dual Core SoC
– 300-MHz ARM926EJ-S™ RISC MPU
– 300-MHz C674x VLIW DSP
· ARM926EJ-S Core
– 32-Bit and 16-Bit (Thumb®) Instructions
– DSP Instruction Extensions
– Single Cycle MAC
– ARM® Jazelle® Technology
– EmbeddedICE-RT™ for Real-Time Debug
· ARM9 Memory Architecture
· C674x Instruction Set Features
– Superset of the C67x+™ and C64x+™ ISAs
– 2400/1800 C674x MIPS/MFLOPS
– Byte-Addressable (8-/16-/32-/64-Bit Data)
– 8-Bit Overflow Protection
– Bit-Field Extract, Set, Clear
– Normalization, Saturation, Bit-Counting
– Compact 16-Bit Instructions
· C674x Two Level Cache Memory Architecture
– 32K-Byte L1P Program RAM/Cache
– 32K-Byte L1D Data RAM/Cache
– 256K-Byte L2 Unified Mapped RAM/Cache
– Flexible RAM/Cache Partition (L1 and L2)
– 1024K-Byte Boot ROM
· Enhanced Direct-Memory-Access Controller 3 (EDMA3): – 2 Channel Controllers
– 3 Transfer Controllers
– 64 Independent DMA Channels
– 16 Quick DMA Channels
– Programmable Transfer Burst Size
· TMS320C674x Floating-Point VLIW DSP Core
– Load-Store Architecture With Non-Aligned Support
– 64 General-Purpose Registers (32 Bit)
– Six ALU (32-/40-Bit) Functional Units
· Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
· Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks
· Supports up to Two Floating Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle – Two Multiply Functional Units
· Mixed-Precision IEEE Floating Point
Multiply Supported up to:
– 2 SP x SP -> SP Per Clock
– 2 SP x SP -> DP Every Two Clocks
– 2 SP x DP -> DP Every Three Clocks
– 2 DP x DP -> DP Every Four Clocks
· Fixed Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples
– Instruction Packing Reduces Code Size
– All Instructions Conditional
– Hardware Support for Modulo Loop Operation
– Protected Mode Operation
– Exceptions Support for Error Detection and Program Redirection
· Software Support
– TI DSP/BIOS™
– Chip Support Library and DSP Library
· 128K-Byte RAM Shared Memory
· 1.8V or 3.3V LVCMOS IOs (except for USB and DDR2 interfaces)
· Two External Memory Interfaces:
– EMIFA
· NOR (8-/16-Bit-Wide Data)
· NAND (8-/16-Bit-Wide Data)
· 16-Bit SDRAM With 128 MB Address Space
– DDR2/Mobile DDR Memory Controller
· 16-Bit DDR2 SDRAM With 512 MB Address Space or
· 16-Bit mDDR SDRAM With 256 MB Address Space
· Three Configurable 16550 type UART Modules:
– With Modem Control Signals
– 16-byte FIFO
– 16x or 13x Oversampling Option
· LCD Controller
· Two Serial Peripheral Interfaces (SPI) Each With Multiple Chip-Selects
· Two Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO) Interfaces
· Two Master/Slave Inter-Integrated Circuit (I2C Bus™)
· One Host-Port Interface (HPI) With 16-Bit-Wide Muxed Address/Data Bus For High Bandwidth
· Programmable Real-Time Unit Subsystem (PRUSS)
– Two Independent Programmable Realtime Unit (PRU) Cores
· 32-Bit Load/Store RISC architecture
· 4K Byte instruction RAM per core
· 512 Bytes data RAM per core
· PRU Subsystem (PRUSS) can be disabled via software to save power
· Register 30 of each PRU is exported from the subsystem in addition to the normal R31 output of the PRU cores.
– Standard power management mechanism
· Clock gating
· Entire subsystem under a single PSC clock gating domain
– Dedicated interrupt controller
– Dedicated switched central resource
· USB 1.1 OHCI (Host) With Integrated PHY (USB1)
· USB 2.0 OTG Port With Integrated PHY (USB0)
– USB 2.0 High-/Full-Speed Client
– USB 2.0 High-/Full-/Low-Speed Host
– End Point 0 (Control)
– End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) Rx and Tx
· One Multichannel Audio Serial Port:
– Transmit/Receive Clocks up to 50 MHz
– Two Clock Zones and 16 Serial Data Pins
– Supports TDM, I2S, and Similar Formats
– DIT-Capable
– FIFO buffers for Transmit and Receive
· Two Multichannel Buffered Serial Ports:
– Transmit/Receive Clocks up to 50 MHz
– Two Clock Zones and 16 Serial Data Pins
– Supports TDM, I2S, and Similar Formats
– AC97 Audio Codec Interface
– Telecom Interfaces (ST-Bus, H100)
– 128-channel TDM
– FIFO buffers for Transmit and Receive
· 10/100 Mb/s Ethernet MAC (EMAC):
– IEEE 802.3 Compliant
– MII Media Independent Interface
– RMII Reduced Media Independent Interface
– Management Data I/O (MDIO) Module
· Video Port Interface (VPIF):
– Two 8-bit SD (BT.656), Single 16-bit or Single Raw (8-/10-/12-bit) Video Capture Channels
– Two 8-bit SD (BT.656), Single 16-bit Video Display Channels
· Universal Parallel Port (uPP):
– High-Speed Parallel Interface to FPGAs and Data Converters
– Data Width on Each of Two Channels is 8- to 16-bit Inclusive
– Single Data Rate or Dual Data Rate Transfers
– Supports Multiple Interfaces with START, ENABLE and WAIT Controls
· Serial ATA (SATA) Controller:
– Supports SATA I (1.5 Gbps) and SATA II (3.0 Gbps)
– Supports all SATA Power Management Features
– Hardware-Assisted Native Command Queueing (NCQ) for up to 32 Entries
– Supports Port Multiplier and Command-Based Switching
· Real-Time Clock With 32 KHz Oscillator and Separate Power Rail
· Three 64-Bit General-Purpose Timers (Configurable as Two 32-Bit Timers)
· One 64-Bit General-Purpose Timer (Watch Dog)
· Two Enhanced Pulse Width Modulators (eHRPWM):
– Dedicated 16-Bit Time-Base Counter With Period And Frequency Control
– 6 Single Edge, 6 Dual Edge Symmetric or 3 Dual Edge Asymmetric Outputs
– Dead-Band Generation
– PWM Chopping by High-Frequency Carrier
– Trip Zone Input
· Three 32-Bit Enhanced Capture Modules (eCAP):
– Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) outputs
– Single Shot Capture of up to Four Event Time-Stamps
· 361-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZCE Suffix], 0.65-mm Ball Pitch
· 361-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZWT Suffix], 0.80-mm Ball Pitch
Click to view :
OMAP-L138.pdf
