TMP  -  Series DataSheet
TMPR4955C  -  64-Bit TX System RISC TX49 Family   -  TOSHIBA Corporation  -  RISC 64Bit

1. Introduction
1.1 Overview
The TMPR4955B and the TMPR4955C (to be called “TX4955” hereinafter) is a standard microcontroller of 64-bit RISC Microprocessor TX49 family.
The TMPR4955B uses the TX49/H3 Processor Core, and the TMPR4955C uses the TX49/H4 Processor Core as the CPUs. The TX49/H3 and the TX49/H4 Processor Cores are 64-bit RISC CPU cores Toshiba developed based on the R4000 architecture of MIPS Technologies, Inc (“MIPS”).
TX4955 supports 32-bit SysAD bus interface which have multiplexed address and data between the processor and an external agent
1.2 Notation Used in this Manual
1.2.1 Numerical Notation
• Hexadecimal numbers in this manual are expressed as follows:0x2A (example shown for decimal number 42)
KB (kilobyte) 210 = 1,024 bytes
MB (megabyte) 220 = 1,024 × 1,024 = 1,048,576 bytes
GB (gigabyte) 230 = 1,024 × 1,024 × 1,024 = 1,073,741,824 bytes
1.2.2 Data Notation
• Byte: Eight bits
• Half word: Two contiguous bytes (16 bits)
• Word: Four contiguous bytes (32 bits) “W” may be used for a word data.
• Double word: Eight contiguous bytes (64 bits) “D” may be used for a double word data.
1.2.3 Signal Notation
• Active-low signals are indicated by adding an asterisk(*) at the end of the signal name (Example: RESET*)
• When a signal is driven to the active voltage level, the signal is said to be “asserted.” When the signal is driven to an inactive voltage level, it is said to be “deasserted.”
1.2.4 Register Notation
• The following nomenclature is used for access attributes.
R: Read only. Cannot be written.
W: Write only. The bit value is undefined if read.
R/W: Read/Write

2. Features
• TX49/H3 Processor Core and TX49/H4 Processor Core
TX49/H3 Processor Core and TX49/H4 Processor Core are 64-bit RISC CPU cores Toshiba developed based on the architecture of MIPS for interactive consumer applications including Printer, Network and set-top terminals.
• Internal bus width is 64-bit, External bus width is 32-bit.
Core and Cache are connected with 64-bit internal bus. External bus is 32-bit SysAD-bus I/F with multiplexed address and data. This interface is compatible with the R4300, and R5000 system interfaces.
• Power management
Product Name Internal Supply Voltage External Supply Voltage (I/O)
TMPR4955B 1.5 V 3.3 V
TMPR4955C 1.25 V 3.3 V or 2.5 V
The TX4955 supports Power management mode (Halt, Doze)
• Maximum operating frequency
The SysAD-bus I/F and Processor’s maximum operating frequency is set by External pin (DivMode[2:0]).
Div Mode[2:0] EC-bit Clock Ratio Supplementation
000 010 1:4
001 111 1:2.5
010 000 1:2
011 001 1:3
100 100 1:3.5 TMPR4955C only
101 101 1:4.5
110 110 1:5
111 011 1:6 TMPR4955C only
• Package
160-pin QFP
• Part Number
TMPR4955BFG-200: Maximum internal operating frequency = 200 MHz
TMPR4955BFG-300: Maximum internal operating frequency = 300 MHz
TMPR4955CFG-400: Maximum internal operating frequency = 400 MHz
(Ask your nearest Toshiba sales representative for the latest part number.)