Features
High-Performance, Low-Power, Fixed-Point TMS320C55x Digital Signal Processor (DSP)
− 6.25-/5-ns Instruction Cycle Time
− 160-/200-MHz Clock Rate
− One/Two Instructions Executed per Cycle
− Dual Multipliers (Up to 400 Million Multiply-Accumulates Per Second (MMACS))
− Two Arithmetic/Logic Units
− One Internal Program Bus
− Three Internal Data/Operand Read Buses
− Two Internal Data/Operand Write Buses
Instruction Cache (24K Bytes)
160K x 16-Bit On-Chip RAM Composed of:
− Eight Blocks of 4K × 16-Bit Dual-Access RAM (DARAM) (64K Bytes)
− 32 Blocks of 4K × 16-Bit Single-Access RAM (SARAM) (256K Bytes)
16K × 16-Bit On-Chip ROM (32K Bytes)
8M × 16-Bit Maximum Addressable
External Memory Space
32-Bit External Memory Interface (EMIF) With Glueless Interface to:
− Asynchronous Static RAM (SRAM)
− Asynchronous EPROM
− Synchronous DRAM (SDRAM)
− Synchronous Burst SRAM (SBSRAM)
Programmable Low-Power Control of Six
Device Functional Domains
On-Chip Peripherals
− Two 20-Bit Timers
− Six-Channel Direct Memory Access (DMA) Controller
− Three Multichannel Buffered Serial Ports (McBSPs)
− 16-Bit Parallel Enhanced Host-Port Interface (EHPI)
− Programmable Digital Phase-Locked Loop (DPLL) Clock Generator
− Eight General-Purpose I/O (GPIO) Pins and Dedicated General-Purpose Output (XF)
On-Chip Scan-Based Emulation Logic
IEEE Std 1149.1† (JTAG) Boundary Scan Logic
240-Terminal MicroStar BGA (Ball Grid Array) (GGW Suffix)
240-Terminal MicroStar BGA (Ball Grid Array) (ZGW Suffix) [Lead-Free]
3.3-V I/O Supply Voltage
1.6-V Core Supply Voltage
Description
The TMS320VC5510/5510A (5510/5510A) fixed-point digital signal processors (DSPs) are based on the TMS320C55x DSP generation CPU processor core. The C55x?DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform up to two data transfers per cycle independent of the CPU activity.
The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the address unit (AU) and data unit (DU) of the C55x CPU.
The C55x? DSP generation supports a variable byte width instruction set for improved code density. The instruction unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the program unit (PU). The program unit decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions. The 5510/5510A also includes a 24K-byte instruction cache to minimize external memory accesses, improving data throughput and conserving system power.
The 5510/5510A peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM and synchronous burst SRAM. Three full-duplex multichannel buffered serial ports (McBSPs) provide glueless interface to a variety of industry-standard serial devices, and multichannel communication with up to 128 separately enabled channels. The enhanced host-port interface (EHPI) is a 16-bit parallel interface used to provide host processor access to internal memory on the 5510/5510A. The EHPI can be configured in either multiplexed or non-multiplexed mode to provide glueless interface to a wider variety of host processors. The DMA controller provides data movement for six independent channel contexts without CPU intervention, providing DMA throughput of up to two 16-bit words per cycle. Two general-purpose timers, eight general-purpose I/O (GPIO) pins, and digital phase-locked loop (DPLL) clock generation are also included.
The 5510/5510A is supported by the industry’s leading eXpressDSP? software environment including the Code Composer Studio?integrated development environment, DSP/BIOS? software kernel foundation, the TMS320? DSP Algorithm Standard, and the industry’s largest third-party network. Code Composer Studio features code generation tools including a C-Compiler, Visual Linker, simulator, Real-Time Data Exchange (RTDX?), XDS510? emulation device drivers, and Chip Support Libraries (CSL). DSP/BIOS is a scalable real-time software foundation available for no cost to users of Texas Instruments’ DSP products providing a pre-emptive task scheduler and real-time analysis capabilities with very low memory and megahertz overhead. The TMS320 DSP Algorithm Standard is a specification of coding conventions allowing fast integration of algorithms from different teams, sites, or third parties into the application framework. Texas Instruments’ extensive DSP third-party network of over 400 providers brings focused competencies and complete solutions to customers.
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TMS320VC5510AGGWA2.pdf
