GENERAL DESCRIPTION
W9864G2GH is a high-speed synchronous dynamic random access memory (SDRAM), organized as 512K words × 4 banks × 32 bits. Using pipelined architecture and 0.11 μm process technology, W9864G2GH delivers a data bandwidth of up to 800M bytes per second. For different application, W9864G2GH is sorted into the following speed grades: -5/-6/-6C/-6I and -7.The -5 parts can run up to 200MHz/CL3.The -6/-6C/-6I parts can run up to 166 MHz/CL3. (The grade of –6C with tCK=7.5nS on CL=2, tIH=0.8nS on CL=2/3 and the -6I grade which is guaranteed to support -40°C ~ 85°C.) The -7 parts can run up to 143 MHz/CL3.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W9864G2GH is ideal for main memory in high performance applications.
FEATURES
• 3.3V± 0.3V for -5/-6/-6I grade power supply
2.7V??3.6V for -6C/-7 grade power supply
2.3V??2.7V, @ tCK >10nS for -6C grade power supply
• Up to 200 MHz Clock Frequency
• 524,288 words × 4 banks × 32 bits organization
• Self Refresh Current: Standard and Low Power
• CAS Latency: 2 & 3
• Burst Length: 1, 2, 4, 8 and full page
• Sequential and Interleave Burst
• Byte data controlled by DQM0-3
• Auto-precharge and controlled precharge
• Burst read, single write operation
• 4K refresh cycles/64 mS
• Interface: LVTTL
• Packaged in TSOP II 86-pin , using Lead free materials with RoHS compliant
Click to view :
W9864G2GH-6.pdf
